With higher integration of memories, there have recently been made a variety of requests to semiconductor device by users, for example, high speed response, reduction of electric power consumption, widening of output word structure and enlargement of package variation. For coping with these various requests, package designing should be made flexibly.
In order to satisfy the above-mentioned requests, semiconductor devices of LOC (Lead On Chip) structure have been proposed, as described in for example "Nikkei Microdevices" (pp. 89-97, February, 1991) and Japanese Patent Laid-Open Publication No. 246125/1990. The LOC structure has various advantages such as minimized size, high speed response, reduced noise and easy layout, and hence it is said that the LOC structure is most strikingly adopted to large-scale semiconductor devices which are expected to be developed in future.
In the LOC structure, as shown in FIG. 7, plural inner leads of a semiconductor device lead frame (referred to as "lead frame" hereinafter) are fixed onto a surface of a chip, on which a circuit has been formed, by way of insulating tapes which electrically insulate the inner leads from the chip, and the inner leads are electrically connected with the chip by a bonding wire. The semiconductor device is sealed with a molding resin, and the back surface of the chip is in contact with the molding resin.
The LOC structure has various advantages as described above, but this structure involves problems which must be solved because it is entirely different from structures of conventional packages. One of problems which must be solved is lowering of reliability caused by separation between the chips and the molding resin, occurrence of package cracks, etc.
The lowering of reliability caused by occurrence of package cracks, etc. is not an inherent problem in the semiconductor device having the LOC structure, and it is a very serious problem to all the semiconductor devices having such structures as shown in FIGS. 8 to 9 wherein the back surface of the chip is partially or wholly in contact with the molding resin. FIG. 8 shows a semiconductor device having such a structure that a die pad has a slit. FIG. 9 shows a semiconductor device having a COL (Chip On Lead) structure.
The mechanism of the separation between the chips and the molding resin or the occurrence of package cracks has been diversely reported so far.
One of the mechanism of these phenomena is an invasion of moisture into the IC package.
The invasion routes of moisture into the IC package are broadly classified as follows:
(1) invasion through interface between the lead frame and the resin, PA1 (2) invasion through interface between the resin and a filler filled in the resin, and PA1 (3) invasion through the resin bulk. PA1 wherein the radiation curable adhesive layer comprises 100 parts by weight of an acrylic adhesive composed of a copolymer of an acrylic ester and an OH group-containing polymerizable monomer and PA1 50-200 parts by weight of a radiation polymerizable compound having two or more unsaturated bonds, and PA1 the radiation curable adhesive layer has an elastic modulus of not less than 1.times.10.sup.9 dyn/cm.sup.2 after curing by irradiation with radiation.
These invasions are caused by capillarity or diffusion, and as the environmental temperature or humidity at which the IC package is left rises, the IC package absorbs moisture more easily. Further, as the environmental temperature rises, the moisture diffusion rate at the initial stage becomes higher and the moisture absorption reaches its saturation point more rapidly. For example, there is a report that when the IC package is allowed to stand at 85.degree. C. and 85% RH (RH: relative humidity) and to absorb moisture, the moisture absorption reaches 80 to 90% of its saturation point in about 168 hours. Moreover, even in an ordinary atmosphere of an ordinary temperature and 75% RH, moisture easily permeates the molding resin material of the IC package, for example, an epoxy resin.
In the IC package such as SOJ or QFP, soldering is conducted generally by means of IR reflowing in which heating is effected by infrared rays or vapor reflowing in which an inert liquid is vaporized and the IC package is exposed to the vapor of high temperature since both reflowing methods are suitable for mass production. In the IR reflowing, the former method, the IC package is exposed to a high temperature of 240 to 250.degree. C., whereby the moisture which has invaded inside of the IC package as described above is explosively expanded by the high temperature during the reflowing operation, and thereby water vapor pressure is applied onto the interface between the epoxy resin and the lead frame to bring about interfacial separation therebetween. As a result, package cracks take place.
The package cracks caused by the IR reflowing are often observed even when the package is allowed to stand at an ordinary temperature for about 168 hours, though it depends on the shape of the lead frame in the package, the surface area of the chips, etc.
One reason for promoting the interfacial separation is a decrease of adhesion strength between the resin material used for sealing the package, for example, an epoxy resin, and the contact surface of the chip. The adhesion strength is largely influenced by cleanliness of the adherend surface. For example, the adhesion strength is very sensitive even to a foreign substance having an angstrom level thickness remaining on the adherend surface so as to decrease the adhesion strength, whereby invasion of moisture or retention thereof within the package is easily made, and finally the package cracks are brought about.
By the way, semiconductor wafers of silicon, gallium-arsenide, etc. are usually produced in relatively large diameter, and the wafers are diced into chips, which are then transferred to the subsequent mounting stage. At this time, the semiconductor wafers are subjected to such operations as dicing, rinsing, drying and irradiation of radiation rays to cure the radiation curing adhesive layer of an adhesive sheet in a state that the semiconductor wafers are adhered to the adhesive sheet. Then, an expansion operation of the adhesive sheet is carried out if necessary, and thereafter operations of picking up the chips and mounting the chips are carried out.
Adhesive sheets which are intended for use in the processing stages of wafers, from the dicing stage up to the pick-up stage, are desired to have an adhesion force sufficient to retain wafers and/or chips thereon in the course from the dicing stage up to the expanding stage, but in the pick-up stage, they are desired to only retain an adhesion force of such an extent that no adhesive remains on the picked-up wafer chips. As such adhesive sheets for applying wafers thereon as mentioned above, those described in for example Japanese Patent Publication No. 56112/1989 have been generally used, and they can be used without any problem in preparing semiconductor devices of conventional type.
However, in the preparation of semiconductor devices having such a structure that the back surfaces of the chips are partially or wholly in contact with the molding resin, a trouble of package crack occurrence is observed and the reliability of the semiconductor device is reduced.